Energy-aware Memory Management for High-end Servers

1 Introduction

Reduce energy consumption becomes an increasingly important issue to support green computing. In recent years, large-scale computation facilities, such as supercomputers and high-end data servers, may consume 100 megawatts of power, In addition, such large power consumption also raises the temperature of hardware components’ through rapid heat dissipation, accordingly increasing the possibility of system’s failure and reducing the system’s availability.

This research work aims to reduce the energy consumption of memory chips on high-end data servers. Measurements from real server systems show that memory can be the dominate energy consumer in a server and consume 50% more power than processors. As a result, the memory power consumption becomes dominated on these servers.

The challenge in memory energy conservation mainly lies in that memory accesses need to be judiciously coordinated to take advantage of the energy-saving features enabled by modern memory chips. Memory chips, such as RAMBUS, can be independently set to an appropriate power state: active, standby, nap, or powerdown. Without coordinating memory accesses, the benefit of such automatic power management is limited. Figure 1 shows an example where four DMA operations are not coordinated and as a result five memory chips are activated concurrently. If these accesses are appropriately coordinated, fewer chips need to be activated simultaneously, as shown in Figure 2.

The long-term research objective of this project is to design energy-aware memory management scheme for high-end servers, which is my Ph.D. dissertation topic. The short-term research objectives over this summer are three folds: 1) develop a trace-driven simulator that can precisely report the total memory energy consumption; 2) evaluate the energy efficiencies of current cache replacement strategies; 3) design a novel energy-aware buffer cache replacement strategy that can cluster memory I/O requests to fewer memory chips.

Figure 1. An example of un-coordinated accesses that activate four memory chips concurrently

Figure 2. An example of coordinated accesses that activate only two memory chips concurrently

2 Stage 1 :Develop trace-driven memory energy simulator

I have developed an energy simulator that models memory access timing by precisely incorporating disks, DMA control, and networking. It serves as the basic research foundation of my Ph.D. dissertation work.

3 Stage 2: Evaluate energy efficiencies of existing memory management policies

Exiting memory management policies, widely used in real systems, have been integrated into the simulator described previously. By running traces collected from real system on this simulator, a comprehensive study on the energy efficiencies of current management schemes have been conducted. Specifically, the following policies will be investigated: LRU, LIRS, ARC, 2Q, LRFU and OPT.

4 Stage 3: Design an energy-efficient buffer cache replacement

In a data server, most of memory chips are used as buffer cache. The data placement and replacement policy determines the access orders to memory chips. In order to save energy consumption, data blocks with high temporal affinity need to be placed into same set of memory chips. As a result, memory access traffics are only directed to a small number of memory chips at same time. However, existing cache replacement cannot faithfully preserve such temporal affinity that widely presents in high-end server workloads. Thus a new buffer cache replacement strategy is needed to temporally align memory accesses to a small set of memory chips. I am planning to design a new replacement strategy that will strike the optimal tradeoff between conserving energy saving and achieving high hit rates.

5 Related Works

Milly Watt project and Power aware virtual memory project proposes to save energy in virtual memory management by judiciously allocating and migrating memory pages, which cluster an application’s pages into a minimal number of chips and ignores the buffer cache memory energy management.

PSALM proposes two schemes to save energy in data servers: temporally aligning DAM transfers to the same memory chips through buffering and migrating data among chips to minimize the number of active chips.

Techniques for Optimizing Power and Energy proposes tracing memory chips activities using LRU to reduce memory energy consumption.

6 Research Benefits

This research project aims to reduce memory consumption and promote green computing.