Phase - Locked Loops

 

This is our final project for ECE 547 -- Digital Phase Locked Loops. The final layout is shown to the left. It consists of two sets of PLLs. One is designed for the input digital signals whose frequecy is around 20MHz, the other is for 25MHz. Each PLL has three major parts -- phase & frequency detector, loop filter and voltage controled oscillator.

 

 

Here is our final report and its contents.

Test results and a a poster describing our project are also available.

If you have any questions, please contact us.

Designer: Fan Yang

Dali Wang

1 August 2002